FIG. 1 is a schematic of a buck SMPC of the related art. The buck SMPC has a control stage 5, a switch stage 15, filter stage 20. An input voltage source 10 such as a battery has a first terminal connected to the input of the switch stage 15. A second terminal of the input voltage source 10 is connected the ground reference voltage source. The control stage 5 provides the necessary signals for activating and deactivating the switch stage 15 to control the current IL applied to the filter stage 20. The control stage 5 has an error amplifier (not shown) that receives a feedback voltage indicative of the output voltage VOUT from the output terminal 25 of the buck SMPC. A target reference voltage source (not shown) provides a target reference voltage to a second input of the error amplifier. The difference between the feedback voltage and the target reference voltage is used to generate an error signal (not shown) indicative of a difference between the output voltage VOUT of the SMPC and the target reference voltage VREF. The target reference voltage is a design voltage level for the output voltage VOUT of the SMPC and thus the control stage 5 is structured to minimize the error signal.
The output of the error amplifier 20 is connected to the input of a pulse width modulation (PWM) generator (not shown). The PWM generator includes a PWM comparator (not shown) and a ramp generator (not shown). The PWM comparator receives the error signal at a noninverting input and a ramp clocking signal as created by the ramp generator at the inverting input. The PWM comparator compares the error signal and the ramp clocking signal and generates a digital PWM signal at the output of the PWM comparator. When the error signal applied to the noninverting input of the comparator is less than the ramp clocking signal applied to the inverting input, the digital PWM signal will be logical (0). As soon as the ramp clocking signal becomes larger than the error signal the digital PWM signal will be logical (1). The ramp clocking signal generates the digital PWM signal that has a pulse width proportional to VOUT at equilibrium condition and is based the error signal.
The digital PWM signal is further conditioned to generate the drive signals φ1 and φ2 that are applied to control the switch transistors MP1 and MN1 of the switch stage 15. The switch transistor MN has a source connected to the first terminal of the input voltage source 10 and a gate connected to the receive the drive signal φ1. The switch transistor MN1 has a drain connected to the drain of the switch transistor MP1 and to the output terminal of the switch stage 15. The switch transistor MP1 has a gate connected to receive the drive signal φ1 and the switch transistor MN1 has a gated connected to receive the drive signal φ2. The output terminal of the switch stage 15 is connected to the input terminal of the filter stage 20 and thus to a first terminal of an inductor L. The second terminal of the inductor L is connected to the first plate of the capacitor CL and to the output terminal 25 of the filter stage 20. The output terminal 25 of the filter stage 20 is connected to the load resistance RLOAD. The load current ILOAD is the current flowing through the output terminal 25 to the load resistance RLOAD.
FIG. 2 is a schematic of a multiple phase buck switch mode power converter of the related art. The switched-mode converter circuit is structured as a multiphase buck switched-mode converter. The multiphase buck SMPC has a control circuit 105, multiple power stages 115a, . . . , 115n, and a filter stage 120. The control circuit 105 receives a feedback voltage indicative of the output voltage VOUT from the output terminal 125 of the multiple stage buck SMPC. The control circuit 105 compares the feedback voltage with a reference voltage and determines and error signal. The error voltage as described above for the single phase buck SMPC is compared with a target reference voltage to determine the difference between the feedback voltage and the target reference voltage to generate the error signal that is indicative of a difference between the output voltage VOUT of the SMPC and the target reference voltage VREF. The target reference voltage is a design voltage level for the output voltage VOUT of the SMPC and thus the control stage 105 is structured to minimize the error signal.
The error signal is transferred to a multiple pulse width modulation circuits. Each pulse width modulation circuit is associated with one of the power stages 115a, . . . , 115n. The pulse width modulation circuits each generate the drive signals φ11, φ12, . . . , φ1n, φ1n that are each applied to control the switch transistors MP1 and MN1 of one of the multiple power stages 115a, . . . , 115n. 
The switch transistors MP1 each have a source that is connected to the first terminal of the input voltage source 110. Each of the gates of the switch transistors MP1 and MN1 are connected to receive the designated drive signals φ11, φ12, . . . , φ1n, 1n for controlling the current flow through the inductor L of the associated phase of the multiple power stages 115a, . . . , 115n. The drains of the switch transistors MP1 and MN1 are connected together and to the first terminal of the inductor L. The sources of the switch transistors MN1 are connected to the ground reference voltage source.
The filter stage is essentially distributed among each of the multiple power stages 115a, . . . , 115n. Each of the multiple power stages 115a, . . . , 115n has one of the multiple stage inductors L1, . . . , Ln where a first terminal of each of the inductors L1, L2, . . . , Ln is connected to one the common connection of the drains of the switching transistors MP1 and MN1 of the multiple power stages 115a, . . . , 115n. The second terminals of the inductors L1, L2, . . . , Ln are commonly connected together and to the first plate of a load capacitor CL, thus forming the filter stage. The second plate of the load capacitor CL is connected to the ground reference voltage source. The commonly connected second terminals of the inductors L1, L2, . . . , Ln and the first plate of the load capacitor CL are connected to the load resistance RLOAD through the output terminal 125. The load current ILOAD is the current flowing through the output terminal 125 to the load resistance RLOAD. The load current ILOAD is the total current from each of the multiple power stages 115a, . . . , 115n. 
The control stages 5 and 105 of respectively of FIGS. 1 and 2 in various implementations have other control circuitry for providing compensation signals and other control function for improving noise immunity, energy efficiency, and other operational improvements. Some of these implementations require measurement of the inductor current and the load current. Various techniques for these measurements are known in the art. Some methods are direct measurements by placing known resistors in the current paths and determining the current flow by determining a voltage drop across the resistor. However, this technique is a problem in integrated circuits, in that the resistance increases power consumption and added voltage drop in the network.
Sensorless current mode (SCM) control is an observer method that provides the operating benefits of current mode control without current physical sensing, as described in “Sensorless Current Mode Control-an Observer-Based Technique for DC-DC Converters,” Midya, et al., IEEE Transactions on Power Electronics, vol. 16, no. 4, pp. 522-526, July 2001, found 8/10/13 at http://ieeexplore.ieee.org/stamp/stamp.jsp? tp=&arnumber=931070&isnumber=20140. The observer method constructs a model of the system to be controlled, and then uses state information from the model. In sensorless current mode (SCM) control, an inductor current IL is reconstructed from voltage information. The inductor voltage in a SMPC is usually a far larger signal than the output of a current sensor, and its range does not change much as a function of loading. In its simplest form, the SCM control approach reconstructs an inductor current directly by integrating the inductor voltage.
The voltage drop across the SMPC inductor L is determined and is used to calculate the output current ILOAD using the integration. A mirrored current of the output device is created, and sensed for both NMOS and PMOS currents and then combined. This approach includes the current ripple that needs to be averaged. The integration of the voltage information is used to reconstruct the inductor current. This technique of using a sensorless current sensing scheme results in a slow response time for generating the average current information.